Fbar structure having single crystalline piezoelectric layer and fabricating method thereof

ABSTRACT

A film bulk acoustic resonator (FBAR) structure includes a bottom cap wafer, a piezoelectric layer disposed on the bottom cap wafer, the piezoelectric layer including a single crystalline piezoelectric material, a bottom electrode disposed below the piezoelectric layer; a top electrode disposed above the piezoelectric layer; and a cavity disposed below the bottom electrode.

FIELD OF THE DISCLOSURE

The present disclosure relates to the field of semiconductor devicesand, in particular, to a film bulk acoustic resonator (FBAR) structurehaving a single crystalline piezoelectric layer and a method offabricating such a FBAR structure.

BACKGROUND

A film bulk acoustic resonator (FBAR) is a device including a thin filmthat is made of a piezoelectric material and disposed between twoelectrodes. The FBAR device is typically fabricated using semiconductormicro-processing technology.

Due to its small thickness, the FBAR device may be used in applicationsrequiring high frequency, small size, and light weight. An exemplaryapplication of the FBAR device is a filter used in mobile communicationdevices.

The FBAR device usually includes a piezoelectric layer grown on asilicon substrate. However, due to the lattice mismatch between thepiezoelectric layer and the silicon substrate, the quality of thepiezoelectric layer may not be high enough for achieving superiorperformance of the FBAR device.

Therefore, there is a need for a large-scale commercial mass productionsolution for producing a high-quality piezoelectric layer.

SUMMARY

Embodiments of the present disclosure provide a film bulk acousticresonator (FBAR) structure. The FBAR structure may include a bottom capwafer; a piezoelectric layer disposed on the bottom cap wafer, thepiezoelectric layer including a single crystalline piezoelectricmaterial; a bottom electrode disposed below the piezoelectric layer; atop electrode disposed above the piezoelectric layer; and a cavitydisposed below the bottom electrode.

The single crystalline piezoelectric material may have a crystallinityof less than 0.5 degrees at Full Width Half Maximum (FWHM) measuredusing X-ray diffraction (XRD).

The single crystalline piezoelectric material may include aluminumnitride (AlN), aluminum nitride doped with scandium (ScAlN), zinc oxide(ZnO), or lead zirconate titanate (PZT).

The FBAR structure may further include a first insulating layer disposedbelow the cavity; a second insulating layer disposed above the bottomcap wafer; and a metal bonding layer bonding the first insulating layerwith the second insulating layer.

The metal bonding layer may include at least a first metal bonding layerand a second metal bonding layer.

A combination of materials of the first metal bonding layer and thesecond metal bonding layer may be selected from a group of gold-gold(Au—Au), aluminum-copper (Al—Cu), copper-copper (Cu—Cu), gold-silver(Au—Ag), copper-tin (Cu—Sn), aluminum-germanium (Al—Ge), gold-silicon(Au—Si), gold-germanium (Au—Ge), gold-tin (Au—Sn), copper-tin (Cu—Sn),and gold-indium (Au—In).

The FBAR structure may further include a ground contact layerelectrically connecting the metal bonding layer to ground.

The FBAR structure may further include a ground contact window formed inthe first insulating layer and the piezoelectric layer, and exposing themetal bonding layer. The ground contact layer may be electricallyconnected to the metal bonding layer via the ground contact window.

The first insulating layer and the second insulating layer may includesilicon oxide (SiO₂) or silicon carbide (SiC).

The FBAR structure may further include a top passivation layer disposedabove the top electrode, and a bottom passivation layer disposed belowthe bottom electrode.

The top passivation layer and the bottom passivation layer may includesilicon nitride (SiN) or aluminum nitride (AlN).

The FBAR structure may further include a boundary layer surrounding thecavity.

The boundary layer may include silicon (Si), silicon nitride (SiN),aluminum nitride (AlN), polysilicon, amorphous silicon, or a stackedcombination of two or more of those materials.

The FBAR structure may further include a bottom electrode contact layerelectrically connected with the bottom electrode, and a top electrodecontact layer electrically connected with the top electrode.

The FBAR structure may further include a bottom electrode contact windowformed in the piezoelectric layer and exposing the bottom electrode. Thebottom electrode contact layer may be electrically connected with thebottom electrode via the bottom electrode contact window.

Each one of the bottom electrode contact layer and the top electrodecontact layer may include aluminum (Al), copper (Cu), gold (Au),titanium (Ti), tungsten (W), platinum (Pt), or a stacked combination oftwo or more of those materials.

Each one of the top electrode and the bottom electrode may includemolybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum(Ta), tungsten (W), palladium (Pd), ruthenium (Ru), or a stackedcombination of two or more of those materials.

The bottom cap wafer may include silicon (Si), silicon carbide (SiC),sapphire (Al₂O₃), or a stacked combination of two or more of thosematerials.

A projection of at least one side of the bottom electrode may be locatedwithin the cavity.

A projection of at least one edge of the top electrode may be locatedwithin the cavity.

Embodiments of the present disclosure also provide a method forfabricating a film bulk acoustic resonator (FBAR) structure. The methodmay include obtaining a substrate; growing a buffer layer on the wafer;growing an epitaxial layer on the buffer layer; and growing apiezoelectric layer on the epitaxial layer.

A lattice structure of a material of the buffer layer may match alattice structure of a material of the epitaxial layer, and the latticestructure of the material of the epitaxial layer may match a latticestructure of a material of the piezoelectric layer.

The substrate may be formed of silicon (Si), silicon carbide (SiC), orsapphire (Al₂O₃).

The buffer layer may be formed of gallium nitride (GaN), or aluminumnitride (AlN).

The buffer layer may be grown on the wafer by using a metal organicchemical vapor deposition (MOCVD) process.

The epitaxial layer may be formed of gallium nitride (GaN), or aluminumnitride (AlN).

The epitaxial layer may be grown on the buffer layer by using a MOCVDprocess.

The method may further include forming a bottom electrode on thepiezoelectric layer; forming a sacrificial island on the bottomelectrode; and forming a boundary layer on the sacrificial island.

The method may further include forming a first insulating layer on theboundary layer.

The method may further include providing a bottom cap wafer with asecond insulating layer formed on the bottom cap wafer; and bonding thesecond insulating layer with the first insulating layer via a metalbonding layer.

The method may further include removing the wafer, the buffer layer, andthe epitaxial layer to expose a surface of the piezoelectric layer.

The method may further include forming a top electrode on the exposedsurface of the piezoelectric layer.

The method may further include forming a top passivation layer on thetop electrode; forming a top electrode window in the top passivationlayer to expose the top electrode; and forming a top electrode contactlayer in the top electrode window to electrically connect to the topelectrode.

The method may further include forming a ground contact window in thefirst insulating layer and the piezoelectric layer to expose the metalbonding layer; and forming a ground contact layer in the ground contactwindow to electrically connect to the metal bonding layer.

The method may further include forming a bottom electrode contact windowin the piezoelectric layer to expose the bottom electrode; and forming abottom electrode contact layer in the bottom electrode contact window toelectrically connect to the bottom electrode.

The method may further include removing the sacrificial island to form acavity.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this application, illustrate disclosed embodiments and, togetherwith the description, serve to explain the disclosed embodiments.

FIG. 1 is a cross-sectional view of a film bulk acoustic resonator(FBAR) structure, according to an embodiment of the present disclosure.

FIG. 2 is a flow chart of a process of fabricating a FBAR structureaccording to an embodiment of the present invention.

FIGS. 3-15 are cross-sectional views of structures formed in the processof FIG. 2, according to embodiments of the present disclosure.

DETAILED DESCRIPTION

The text below provides a detailed description of the present disclosurein conjunction with specific embodiments illustrated in the attacheddrawings. However, these embodiments do not limit the presentdisclosure. The scope of protection for the present disclosure coverschanges made to the structure, method, or function by persons havingordinary skill in the art on the basis of these embodiments.

To facilitate the presentation of the drawings in the presentdisclosure, the sizes of certain structures or portions may be enlargedrelative to other structures or portions. Therefore, the drawings in thepresent disclosure are only for the purpose of illustrating the basicstructure of the subject matter of the present disclosure. The samenumbers in different drawings represent the same or similar elementsunless otherwise represented.

Additionally, terms in the text indicating relative spatial position,such as “front,” “back,” “upper,” “lower,” “above,” “below,” and soforth, are used for explanatory purposes in describing the relationshipbetween a unit or feature depicted in a drawing and another unit orfeature therein. Terms indicating relative spatial position may refer topositions other than those depicted in the drawings when a device isbeing used or operated. For example, if a device shown in a drawing isflipped over, a unit which is described as being positioned “below” or“under” another unit or feature will be located “above” the other unitor feature. Therefore, the illustrative term “below” may includepositions both above and below. A device may be oriented in other ways(e.g., rotated 90 degrees or facing another direction), and descriptiveterms that appear in the text and are related to space should beinterpreted accordingly. When a component or layer is said to be “above”another member or layer or “connected to” another member or layer, itmay be directly above the other member or layer or directly connected tothe other member or layer, or there may be an intermediate component orlayer.

A traditional fabrication method for a bulk acoustic wave (BAW) filteruses silicon as a substrate, grows an electrode layer on the siliconsubstrate, and grows a piezoelectric layer, such as aluminum nitride(AlN), etc., on the electrode layer. Then, etching and wafer bondingprocesses are performed to form cavities and resonators. However, thelattice structures of silicon, the electrode material of the electrodelayer, and the piezoelectric material of the piezoelectric layer, maynot be matched. For example, molybdenum (Mo), which is commonly used asthe electrode material, has a body-centered cubic (BCC) crystalstructure with a lattice constant of a=3.147 Å, while AlN, which iscommonly used as the piezoelectric material, has a wurtzite structurewith lattice constants of a=3.11 Å, c=4.978 Å. Additionally, theelectrode layer has a polycrystalline structure, and therefore thepiezoelectric layer grown on the electrode layer also has apolycrystalline structure. As a result, the piezoelectric material isusually of low quality, having a crystallinity of more than 1.3 degrees,or even more than 1.6 degrees, at Full Width Half Maximum (FWHM)measured using X-ray diffraction (XRD).

Embodiments of the present disclosure provide a new approach for growingpiezoelectric layer, which includes growing a buffer layer (e.g., AlNbuffer layer) on a silicon wafer, growing an epitaxial layer (e.g., GaNepitaxial layer) on the buffer layer, and growing a piezoelectric layer(e.g., AlN or scandium doped aluminum nitride (ScAlN)) on the epitaxiallayer. GaN has a wurtzite structure having lattice constants of a=3.189Å, c=5.185 Å). Because the GaN lattice structure and lattice constantare very close to those of AlN and ScAlN, and the GaN epitaxial layerhas single crystalline structure, very high quality single crystallineAlN or ScAlN layer can be grown on the GaN epitaxial layer. The singlecrystalline AlN or ScAlN layer grown using the approach according to theembodiments of the present disclosure may have a crystallinity of lessthan 0.5 degrees at FWHM measured using XRD, thereby improving the heatdissipation efficiency of a BAW resonator including such singlecrystalline AlN or ScAlN layer.

On the other hand, the stress of the AlN buffer layer/GaN epitaxiallayer formed on the silicon wafer may be relatively large, resulting inlarge warpage (deformation) of the silicon wafer, causing difficulty ina subsequent SiO₂—Si bonding process, which requires less wafer warpage.According to embodiments of the present disclosure, a metal fusionbonding process, which can tolerate large wafer warpage, is performed toovercome bonding difficulties. However, a metal bonding layer introducedby the metal fusion bonding process, may degrade the performance of theBAW resonator to be significantly. In order to avoid the negativeeffects of the metal bonding layer on the performance of the BAWresonator, the BAW resonator of the embodiments of the presentdisclosure is provided with a grounding through hole to ground the metalbonding layer.

FIG. 1 is a cross-sectional view of a film bulk acoustic resonator(FBAR) structure 1000, according to an embodiment of the presentdisclosure. As illustrated in FIG. 1, FBAR structure 1000 includes abottom cap wafer 200, a piezoelectric layer 120 disposed on bottom capwafer 200, a bottom electrode 130 disposed below piezoelectric layer120, a top electrode 190 disposed above piezoelectric layer 120, and acavity 1000 a disposed below bottom electrode 130. In some embodiments,a projection of at least one edge of bottom electrode 130 is locatedwithin cavity 1000 a. Alternatively or additionally, in someembodiments, a projection of at least one edge of top electrode 190 islocated within cavity 1000 a.

Piezoelectric layer 120 includes a single crystalline piezoelectricmaterial. A crystallinity of the single crystalline piezoelectricmaterial may be less than 0.5 degrees at Full Width Half Maximum (FWHM)measured using X-ray diffraction (XRD). The single crystallinepiezoelectric material may include aluminum nitride (AlN), aluminumnitride doped with scandium (ScAlN), zinc oxide (ZnO), or lead zirconatetitanate (PZT).

Bottom cap wafer 200 may include a material such as, for example,silicon (Si), glass (SiO₂), or sapphire (Al₂O₃).

Top and bottom electrodes 190 and 130 may include any suitableconductive material, including various metal materials with conductiveproperties such as molybdenum (Mo), aluminum (Al), copper (Cu), platinum(Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), etc.,or a stacked combination of two or more of those conductive metalmaterials.

As illustrated in FIG. 1, a top passivation layer 195 is disposed above,and covers a top surface of top electrode 190. A bottom passivationlayer 140 is disposed below, and covers a lower surface of, bottomelectrode 130. Top passivation layer 195 and bottom passivation layer140 may include an electrically insulating material such as siliconnitride (SiN) or aluminum nitride (AlN).

Cavity 1000 a is obtained by removing a sacrificial island (notillustrated in FIG. 1). The sacrificial island may include siliconoxide. A boundary of the removal of the sacrificial island is defined bya boundary layer 160 (also referred-to as an “etch stop layer”), whichis disposed below piezoelectric layer 120 and surrounds the sacrificialisland before the sacrificial island is removed. Boundary layer 160 mayinclude one or more insulating materials such as silicon (Si), siliconnitride (SiN), aluminum nitride (AlN), polysilicon, or amorphoussilicon, or a stacked combination of two or more of those materials.

A first insulating layer 170 is disposed below boundary layer 160. Asecond insulating layer 210 is disposed above bottom cap wafer 200. Ametal bonding layer is disposed between first insulating layer 170 andsecond insulating layer 210 for bonding first insulating layer 170 withsecond insulating layer 210. The metal bonding layer includes at least afirst metal bonding layer 180 and a second metal bonding layer 220. Acombination of the materials of first metal bonding layer 180 and secondmetal bonding layer 220 may be selected from a group of gold-gold(Au—Au), aluminum-copper (Al—Cu), copper-copper (Cu—Cu), gold-silver(Au—Ag), copper-tin (Cu—Sn), aluminum-germanium (Al—Ge), gold-silicon(Au—Si), gold-germanium (Au—Ge), gold-tin (Au—Sn), copper-tin (Cu—Sn),and gold-indium (Au—In). For example, first metal bonding layer 180 maybe formed of Au, and second metal bonding layer 220 may be formed of Au.Alternatively, first metal bonding layer 180 may be formed of Al, andsecond metal bonding layer 220 may be formed of Cu.

A top electrode contact layer 300 is disposed above top passivationlayer 195 and is electrically connected to top electrode 190, via a topelectrode contact window formed through top passivation layer 195. Abottom electrode contact layer 310 is disposed above piezoelectric layer120 and is electrically connected to bottom electrode 130 via a bottomelectrode contact window formed through piezoelectric layer 120. Aground contact layer 320 is disposed above piezoelectric layer 120 andis electrically connected to first metal bonding layer 180 via a contactwindow formed through piezoelectric layer 120, boundary layer 160, andfirst insulating layer 170. Ground contact layer 320 may be connected toground, such that first metal bonding layer 180 is electricallyconnected to ground. Top electrode contact layer 300, bottom electrodecontact layer 310, and ground contact layer 320 may include variousmetals, such as aluminum (Al), copper (Cu), gold (Au), titanium (Ti),tungsten (W), platinum (Pt), etc., or a stacked combination of two ormore of those metals.

FIG. 2 is a flow chart of a process of fabricating a FBAR structureaccording to an embodiment of the present disclosure. FIGS. 3-15 arecross-sectional views of structures formed in steps S1-S13 of theprocess of FIG. 2, according to an embodiment of the present disclosure.

As illustrated in FIG. 3, in step S1, a substrate 100 is obtained. Thematerial of the substrate 100 may be silicon (Si), silicon carbide(SiC), or sapphire (Al₂O₃).

As illustrated in FIG. 4, in step S2, a buffer layer 105 is grown onsubstrate 100 by using, for example, a metal organic chemical vapordeposition (MOCVD) process. Next, an epitaxial layer 110 is grown onbuffer layer 105 by using, for example, a MOCVD process. Afterwards,piezoelectric layer 120 is grown on epitaxial layer 110 by using, forexample, a physical vapor deposition (PVD) process. Buffer layer 105 maybe a single crystal layer, and may be formed of a material having alattice structure that matches the material of epitaxial layer 110 orpiezoelectric layer 120. For example, buffer layer 105 may be formed ofgallium nitride (GaN), or aluminum nitride (AlN), etc. The purpose ofbuffer layer 105 is to grow a high-quality single crystal epitaxiallayer 110. If epitaxial layer 110 is directly grown on substrate 100,epitaxial layer 110 might not have a single crystalline structure due tothe lattice mismatch between the materials of epitaxial layer 110 andsubstrate 100. Epitaxial layer 110 may be formed of a material having alattice structure that matches the material of piezoelectric materiallayer 120. For example, epitaxial layer 110 may be formed of galliumnitride (GaN), or aluminum nitride (AlN), etc. The purpose of epitaxiallayer 110 is to grow a high-quality single crystal piezoelectric layer120. Thus, according to the embodiments of the present disclosure,piezoelectric layer 120 is grown on epitaxial layer 110, which is grownon buffer layer 105 grown on substrate 100, and the lattice structuresof the materials of buffer layer 105 and epitaxial layer 110 match eachother, and match that of piezoelectric layer 120. Therefore,piezoelectric layer 120 formed according to the embodiments of thepresent disclosure may be a high-quality single crystal structure.

In addition, as illustrated in FIG. 4, in step S2, after piezoelectriclayer 120 is obtained, a bottom electrode layer 130 and a bottompassivation layer 140 are sequentially deposited on piezoelectric layer120. The material of bottom electrode layer 130 may be any suitableconductive material, such as various metal materials with conductiveproperties or a stack of several conductive metal materials, such asmolybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum(Ta), tungsten (W), palladium (Pd), ruthenium (Ru), etc. Bottompassivation layer 140 may be made of one or more non-conductivematerials such as silicon nitride (SiN) and aluminum nitride (AlN).

As illustrated in FIG. 5, in step S3, bottom electrode layer 130 andbottom passivation layer 140 are patterned and etched to form bottomelectrode 130 and patterned bottom passivation layer 140. The etchingprocess may be a wet chemical etching process, a plasma port etchingprocess, or a combination thereof. This step allows for precisepatterning of bottom electrode 130 of the FBAR structure.

As illustrated in FIG. 6, in step S4, a sacrificial layer 150 isdeposited on the structure illustrated in FIG. 5. Sacrificial layer 150is used to form cavity 1000 a of the FBAR structure. Sacrificial layer150 may include at least one of various types of silicon oxide material,such as pure silicon oxide, phosphor silicate glass (PSG), boronphosphor silicate glass (BPSG), spin on glass (SOG), or fluorinatedsilicate glass (FSG). Sacrificial layer 150 may be deposited by using achemical vapor deposition (CVD) process, a physical vapor deposition(PVD) process, or a combination of both. After depositing sacrificiallayer 150, a top surface of sacrificial layer 150 may be planarized andpolished by using, for example, a chemical mechanical polishing (CMP)process.

As illustrated in FIG. 7, in step S5, sacrificial layer 150 is patternedand etched to form a sacrificial island 150 a. The material ofsacrificial island 150 a will be removed in a subsequent release etchingprocess, thereby forming cavity 1000 a of the FBAR structure. Theetching process may be a wet chemical etching process, a plasma etchingprocess, or a combination of those two processes.

As illustrated in FIG. 8, in step S6, boundary layer 160 is deposited onthe structure of FIG. 7. A portion of boundary layer 160 that surroundssacrificial island 150 a functions as an etch stop layer during thesubsequent release etching process for removing sacrificial island 150 ato form cavity 1000 a. Boundary layer 160 may include a non-conductivematerials such as silicon (Si), silicon nitride (SiN), aluminum nitride(AlN), polysilicon, amorphous silicon, or a stacked combination of twoor more of those materials.

As illustrated in FIG. 9, in step S7, first insulating layer 170 isdeposited on the structure illustrated in FIG. 8. Then, the top surfaceof first insulating layer 170 is planarized and polished. Firstinsulating layer 170 may be deposited by using a CVD process, a PVDprocess, or a combination of those two processes. The material of firstinsulating layer 170 may be silicon oxide (SiO₂), or silicon carbide(SiC), etc. The surface planarization and polishing may be performed byusing, for example, a CMP process.

As illustrated in FIG. 10, in step S8, first metal bonding layer 180 isdeposited on first insulating layer 170. Before the deposition of firstmetal bonding layer 180, metals such as titanium (Ti) and nickel (Ni)may be formed on first insulating layer 170 in order to increase theadhesion between first insulating layer 170 and first metal bondinglayer 180. First metal bonding layer 180 may include a material thatcorresponds to the material of second metal bonding layer 220 to achievemetal bonding. A combination of the materials of first metal bondinglayer 180 and second metal bonding layer 220 may be selected from agroup of gold-gold (Au—Au), aluminum-copper (Al—Cu), copper-copper(Cu—Cu), gold-silver (Au—Ag), copper-tin (Cu—Sn), aluminum-germanium(Al—Ge), gold-silicon (Au—Si), gold-germanium (Au—Ge), gold-tin (Au—Sn),copper-tin (Cu—Sn), and gold-indium (Au—In). For example, first metalbonding layer 180 may be formed of Au, and second metal bonding layer220 may be formed of Au. Alternatively, first metal bonding layer 180may be formed of Al, and second metal bonding layer 220 may be formed ofCu.

As illustrated in FIG. 11, in step S9, bottom cap wafer 200 is obtained.Second insulating layer 210 and second metal bonding layer 220 aresequentially deposited on bottom cap wafer 200. Before the deposition ofsecond metal bonding layer 220, metals such as titanium (Ti) and nickel(Ni) may be formed on second insulating layer 210 in order to increasethe adhesion between first insulating layer 170 and first metal bondinglayer 180. Bottom cap wafer 200 may include a material such as silicon(Si), carbon silicon (SiC), aluminum oxide, quartz, glass, or sapphire(Al₂O₃). Second insulating layer 210 may be deposited by using a CVDprocess, a PVD process, or a combination of those two processes. Thematerial of second insulating layer 210 may be silicon oxide (SiO₂), orsilicon carbide (SiC), etc. As described previously, second metalbonding layer 220 may include a material that corresponds to thematerial of first metal bonding layer 180 to achieve metal bonding. Acombination of the materials of first metal bonding layer 180 and secondmetal bonding layer 220 may be selected from a group of gold-gold(Au—Au), aluminum-copper (Al—Cu), copper-copper (Cu—Cu), gold-silver(Au—Ag), copper-tin (Cu—Sn), aluminum-germanium (Al—Ge), gold-silicon(Au—Si), gold-germanium (Au—Ge), gold-tin (Au—Sn), copper-tin (Cu—Sn),and gold-indium (Au—In).

As illustrated in FIG. 12, in step S10, the structure illustrated inFIG. 10 is flipped over, and first metal bonding layer 180 and secondmetal bonding layer 220 are bonded together by using a metal bondingprocess. As a result, the structure formed on bottom cap wafer 200 andthe structure formed on substrate 100 are combined. The metal bondingprocess may be achieved by one or more of eutectic bonding, anodicbonding, or thermal compression bonding.

As illustrated in FIG. 13, in step S11, substrate 100, buffer layer 105,and epitaxial layer 110 are removed to expose piezoelectric layer 120.The removal of substrate 100 may be performed by a grinding process. Theremoval of buffer layer 105 and epitaxial layer 110 may be performed bya wet chemical etching process, a plasma dry etching process, or acombination of these two processes.

As illustrated in FIG. 14, in step S12, a top electrode layer 190 isdeposited on piezoelectric layer 120, and top passivation layer 195 isdeposited on top electrode layer 190. The material of top electrodelayer 190 may be any suitable conductive material, such as various metalmaterials with conductive properties or a stack of several conductivemetal materials, such as molybdenum (Mo), aluminum (Al), copper (Cu),platinum (Pt), Tantalum (Ta), tungsten (W), palladium (Pd), ruthenium(Ru), etc. The material of top passivation layer 195 can be siliconnitride (SiN), aluminum nitride (AlN), silicon oxide (SiO₂), siliconoxynitride (SiNO), etc., or a stacked combination of those materials.

As illustrated in FIG. 15, in step S13, top electrode layer 190 and toppassivation layer 195 are patterned by etching, to form patterned toppassivation layer 195, top electrode 190. Then, the patterned toppassivation layer 195, piezoelectric layer 120, boundary layer 160, andfirst insulating layer 170 are patterned by etching, for a top electrodecontact window exposing top electrode 190, a bottom electrode contactwindow exposing bottom electrode 130, and a ground contact windowexposing first metal contact layer 180. In some embodiments, a differentetching sequence may be used to form the contact windows, which is notlimited in the present disclosure. For example, passivation layer 195may be first patterned to form the top electrode contact window; then,piezoelectric layer 120 may be patterned to form the bottom electrodecontact window and a part of the ground contact window; and lastly,boundary layer 160 and first insulating layer 170 are patterned to formthe remaining part of the ground contact window.

Next, top electrode contact layer 300 is formed in the top electrodecontact window to be electrically connected to top electrode 190. Bottomelectrode contact layer 310 is formed in the bottom electrode contactwindow to be electrically connected to bottom electrode 130. Groundcontact layer 320 is formed in the ground contact window to beelectrically connected to first metal bonding layer 180. The purpose ofground contact layer 320 is to connect first metal bonding layer 180 toground, thereby reducing or eliminating parasitic capacitance introducedby first metal bonding layer 180 and second metal bonding layer 220. Thematerial of top electrode contact layer 300, bottom electrode contactlayer 310, and ground contact layer 320 may be metal materials, such asaluminum (Al), copper (Cu), gold (Au), titanium (Ti), tungsten (W),platinum (Pt), etc., or a stacked combination of two or more of thosematerials.

Afterwards, sacrificial island 150 a is etched and released to formcavity 1000 a by using a release etching process. The etching ofsacrificial island 150 a is stopped at boundary layer 160. The releaseetching process may be performed by using hydrofluoric acid solution wetetching, buffered oxide etchant (BOE) solution wet etching, orhydrofluoric acid vapor corrosion, or a combination of those processes.As a result, FBAR structure 1000 illustrated in FIG. 1 is formed.

According to the embodiments of the present disclosure, a high-qualitysingle crystal AlN piezoelectric layer can be obtained by growing a GaNepitaxial layer on a silicon wafer, and then growing the AlNpiezoelectric layer on the GaN epitaxial layer. The high-quality singlecrystal AlN piezoelectric layer improves the heat dissipation efficiencyof a bulk acoustic wave resonator including the same. At the same time,the metal bonding method was selected to overcome the difficulty inbonding caused by the wafer warpage as a result of the introduction ofgallium nitride epitaxial layer. In addition, the metal bonding layer isgrounded in order to avoid the negative impact of the metal bondinglayer on the performance.

Other embodiments of the invention will be apparent to those skilled inthe art from consideration of the specification and practice of theinvention disclosed herein. It is intended that the specification andexamples be considered as exemplary only, with a true scope and spiritof the invention being indicated by the following claims.

What is claimed is:
 1. A film bulk acoustic resonator (FBAR) structure,comprising: a bottom cap wafer; a piezoelectric layer disposed on thebottom cap wafer, the piezoelectric layer including a single crystallinepiezoelectric material; a bottom electrode disposed below thepiezoelectric layer; a top electrode disposed above the piezoelectriclayer; and a cavity disposed below the bottom electrode.
 2. The FBARstructure of claim 1, wherein the single crystalline piezoelectricmaterial has a crystallinity of less than 0.5 degrees at Full Width HalfMaximum (FWHM) measured using X-ray diffraction (XRD).
 3. The FBARstructure of claim 1, wherein the single crystalline piezoelectricmaterial includes aluminum nitride (AlN), aluminum nitride doped withscandium (ScAlN), zinc oxide (ZnO), or lead zirconate titanate (PZT). 4.The FBAR structure of claim 1, further comprising: a first insulatinglayer disposed below the cavity; a second insulating layer disposedabove the bottom cap wafer; and a metal bonding layer bonding the firstinsulating layer with the second insulating layer.
 5. The FBAR structureof claim 4, wherein the metal bonding layer includes at least a firstmetal bonding layer and a second metal bonding layer.
 6. The FBARstructure of claim 5, wherein a combination of materials of the firstmetal bonding layer and the second metal bonding layer is selected froma group of gold-gold (Au—Au), aluminum-copper (Al—Cu), copper-copper(Cu—Cu), gold-silver (Au—Ag), copper-tin (Cu—Sn), aluminum-germanium(Al—Ge), gold-silicon (Au—Si), gold-germanium (Au—Ge), gold-tin (Au—Sn),copper-tin (Cu—Sn), and gold-indium (Au—In).
 7. The FBAR structure ofclaim 4, further comprising a ground contact layer electricallyconnecting the metal bonding layer to ground.
 8. The FBAR structure ofclaim 7, further comprising a ground contact window formed in the firstinsulating layer and the piezoelectric layer, and exposing the metalbonding layer, wherein the ground contact layer is electricallyconnected to the metal bonding layer via the ground contact window. 9.The FBAR structure of claim 4, wherein the first insulating layer andthe second insulating layer include silicon oxide (SiO₂) or siliconcarbide (SiC).
 10. The FBAR structure of claim 1, further comprising: atop passivation layer disposed above the top electrode; and a bottompassivation layer disposed below the bottom electrode.
 11. The FBARstructure of claim 10, wherein the top passivation layer and the bottompassivation layer include silicon nitride (SiN) or aluminum nitride(AlN).
 12. The FBAR structure of claim 1, further comprising a boundarylayer surrounding the cavity.
 13. The FBAR structure of claim 12,wherein the boundary layer includes silicon (Si), silicon nitride (SiN),aluminum nitride (AlN), polysilicon, amorphous silicon, or a stackedcombination of two or more of those materials.
 14. The FBAR structure ofclaim 1, further comprising: a bottom electrode contact layerelectrically connected with the bottom electrode; and a top electrodecontact layer electrically connected with the top electrode.
 15. TheFBAR structure of claim 14, further comprising: a bottom electrodecontact window formed in the piezoelectric layer and exposing the bottomelectrode, wherein the bottom electrode contact layer is electricallyconnected with the bottom electrode via the bottom electrode contactwindow.
 16. The FBAR structure of claim 14, wherein each one of thebottom electrode contact layer and the top electrode contact layerincludes aluminum (Al), copper (Cu), gold (Au), titanium (Ti), tungsten(W), platinum (Pt), or a stacked combination of two or more of thosematerials.
 17. The FBAR structure of claim 1, wherein each one of thetop electrode and the bottom electrode includes molybdenum (Mo),aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W),palladium (Pd), ruthenium (Ru), or a stacked combination of two or moreof those materials.
 18. The FBAR structure of claim 1, wherein thebottom cap wafer includes silicon (Si), silicon carbide (SiC), sapphire(Al₂O₃), or a stacked combination of two or more of those materials. 19.The FBAR structure of claim 1, wherein a projection of at least one edgeof the top electrode is located within the cavity.
 20. The FBARstructure of claim 1, wherein a projection of at least one side of thebottom electrode is located within the cavity.